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TMS320C6000 FAMILY: EMIF
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TMS320C6000 FAMILY: EMIF Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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Need for an EMIF Need for EMIF): Traditional DSP (with noan EMIF
Peripheral/ Memory H/W Interface DSP
When interfacing a slow peripheral/memory to a fast DSP, some hardware interface is required. This hardware interface requires fast components in order to keep up with the DSP.
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Need for an EMIF (II) Need for EMIF): Traditional DSP (with noan EMIF
Peripheral/ Memory H/W Interface DSP
Drawback of the hardware interface:
High cost (additional components). Power consumption. Difficult to debug. Cannot be upgraded. Prone to errors.
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The EMIF The EMIF The EMIF supports a glueless interface to several external devices, including:
Synchronous burst SRAM (SBSRAM). Synchronous DRAM (SDRAM). Asynchronous devices, including SRAM, ROM and FIFO's. An external shared-memory device.
For more information on different memory types see spra631.pdf A detailed description for each memory type interface can be found in:
Asynchronous SRAM: spra542a.pdf Synchronous burst SRAM: spra533.pdf Synchronous DRAM: spra433b.pdf
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The EMIF
The C621x/C671x services requests of the external bus from the The EMIF requestors:
On-chip Enhanced Direct Memory Access (EDMA) controller. External shared-memory device controller.
EMIF L1P Cache
C6000 DSP core Instruction Fetch Other Peripherals Enhanced DMA Controller Instruction Dispatch L2 Memory Instruction Decode Data Path A A Register File Interrupt Selector Power Down Logic Boot Configuration L1D Cache L1 S1 M1 D1 Data Path B B Register File D2 M2 S2 L2
Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
PLL
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MEMORY MAP
Byte Address 0000_0000
64K x 8 Internal
(L2 cache)
External Memory
Async (SRAM, ROM, etc.) Sync (SBSRAM, SDRAM)
0180_0000
On-chip Peripherals
Internal Memory
Unified (data or prog) prog) 4 blocks - each can be RAM or cache
8000_0000 9000_0000 A000_0000 B000_0000 FFFF_FFFF
0 256M x 8 External 1 256M x 8 External 2 256M x 8 External 3 256M x 8 External
Level 1 Cache
4KB Program 4KB Data Not in map
4K P
CPU
4K D
L2 64K
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MEMORY MAP (II)
Description Internal RAM (L2) mem EMIF control regs Cache configuration reg L2 base addr & count regs L1 base addr & count regs L2 flush & clean regs CE0 mem attribute regs CE1 mem attribute regs CE2 mem attribute regs CE3 mem attribute regs HPI control reg McBSP0 regs McBSP1 regs Timer0 regs Timer1 regs Interrupt selector regs EDMA parameter RAM EDMA control regs QDMA regs QDMA pseudo-regs McBSP0 data McBSP1 data CE0, 256 MBytes CE1, 256 MBytes CE2, 256 MBytes CE3, 256 MBytes Origin 0x00000000 0x01800000 0x01840000 0x01844000 0x01844020 0x01845000 0x01848200 0x01848240 0x01848280 0x018482c0 0x01880000 0x018c0000 0x01900000 0x01940000 0x01980000 0x019c0000 0x01a00000 0x01a0ffe0 0x02000000 0x02000020 0x30000000 0x34000000 0x80000000 0x90000000 0xA0000000 0xB0000000 Length 0x00010000 0x00000024 0x00000004 0x00000020 0x00000020 0x00000008 0x00000010 0x00000010 0x00000010 0x00000010 0x00000004 0x00000028 0x00000028 0x0000000c 0x0000000c 0x0000000c 0x00000800 0x00000020 0x00000014 0x00000014 0x04000000 0x04000000 0x10000000 0x10000000 0x10000000 0x10000000 8
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C6211/C6711 EMIF Features
Features Bus Width # Memory Spaces Addressable Space (Mbytes) Synchronous Clocking Width Support Supported Memory Type at CE1 Control Signals Synchronous memory in system Additional registers PDT Support ROM/Flash Asynchronous memory I/O Pipeline SBSRAM C621x / C671x 32 4 512 Independent ECLKIN 8/16/32 All types Mixed all control signals Both SDRAM and SBSRAM SDEXT No Yes Yes Yes
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C6713 EMIF Signals C6211/C6711 EMIF Signals
ECLKIN ECLKOUT ED[31:0] EA[21:2] CE[3:0] BE[3:0] Enhanced data memory controller External memory interface (EMIF) ARDY AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE HOLD HOLDA Control registers BUSREQ MUXed Asynch/SDRAM/SBSRAM control Shared by all external interfaces
Clock signals:
ECLKIN ECLKOUT
Data bus: ED[31:0] Address bus: EA[21:2] Byte enable: BE[3:0] Control signals:
Asynchronous ready. Memory type depending.
Bus arbitration:
Internal peripheral bus
Hold Hold acknowledge. Bus request.
10
For a description of the signals see: \Links\signals.pdf
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C6211/C6711 EMIF Configuration C6211/C6711 EMIF Configuration The following need to be configured when interfacing the DSP to an external device using the EMIF:
(1) Memory space control registers (software):
These registers describe the type and timing of the external memory to be used.
(2) EMIF chip enable (hardware):
There are four chip enable (CE0, CE1, CE2 and CE3) that are used when accessing a specific memory location (e.g. if you try to access memory 0x9000 0000 then CE1 will be activated, see next slide).
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C6211/C6711 EMIF Memory Spaces
Memory Block Description Internal RAM (L2) Reserved EMIF Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt selector Registers EDMA RAM and EDMA Registers Reserved QDMA Registers Reserved MCBSP 0/1 Data Reserved EMIF CE0 EMIF CE1 EMIF CE2 EMIF CE3 Reserved Block Size (Bytes) 64K 24M-64K 256k 256k 256k 256k 256k 256k 256k 256k 256k 64M-256k 52 736M-52 256M 1G 256M 256M 256M 256M 1G HEX Address Range 0000 0000 - 0000 FFFF 0001 0000 - 017F FFFF 0180 0000 - 0183 FFFF 0184 0000 - 0187 FFFF 0188 0000 - 018B FFFF 018C 0000 - 018F FFFF 0190 0000 - 0193 FFFF 0194 0000 - 0197 FFFF 0198 0000 - 019B FFFF 019C 0000 - 019F FFFF 01A0 0000 - 01A3 FFFF 01A4 0000 - 01FF FFFF 0200 0000 - 0200 FFFF 0200 0034 - 2FFF FFFF 3000 0000 - 3FFF FFFF 4000 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - AFFF FFFF B000 0000 - BFFF FFFF C000 0000 - FFFF FFFF
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Memory Space Control Registers
Memory Map
0000_0000
Space Control Registers
Global Control
0180_0000
Peripherals
CE0 Control CE1 Control CE2 Control CE3 Control
SDRAM Control SDRAM Refresh Prd
180_0000 180_0008 180_0004 180_0010 180_0014 180_0018 180_001C
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Memory Space Control Registers C6211/C6711 EMIF EMIF global Global Control (GBLCTL): theRegisters control register configures parameters that are common to all the CE spaces.
Polarity definition (x). Signal enable (x).
31 Rsv
R, +0
16
15
Rsv
R,+0
14
Rsv
R ,+0 W
13
Rsv
R ,+1 W
12
Rsv
R ,+1 W
11
BUSREQ
10
ARDY R,+x
9
8
7
NO HOLD R , +0 W
6
Rsv
R,+1
5
Rsv
R,+1
4
3
2
Rsv
R,+0
1
Rsv
R,+0
0
Rsv
R+ ,0
HOLD HOLDA R,+x R,+x
CLK1EN CLK2EN
R+ ,0
R , +1 W
R , +1 W
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EMIF Registers
Question: Why do we need different spaces? Answer: Different spaces allow different types of devices to be used at the same time.
CE0, CE1, CE2, CE3 space control registers (CECTL): are used to specify the type and the read and write timing used for a particular space.
31 Write setup RW, +1111 15 TA R, +11 14 13 Read strobe RW, +111111 28 27 Write strobe RW, +111111 8 7 MTYPE RW, +0010 22 21 20 19 Read setup RW, +1111 3 Write hold MSB RW, +0 2 0 16 Write hold RW, +11 4
Read hold RW, +011
MTYPE default value is RW, +0000. For C621x/C671x, this field is reserved. R,+0.
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EMIF Registers
Field READ SETUP WRITE SETUP READ STROBE WRITE STROBE READ HOLD WRITE HOLD MTYPE
Description Setup width. Number of clock cycles of setup for address (EA) and byte enables (/BE(0-3)) before read strobe (/ARE) or write strobe (/AWE) falling. On the first access to a CE space, this is also the setup after /CE falling. Strobe width. The width of read strobe (/ARE) and write strobe (/AWE) in clock* cycles. Hold width. Number of clock cycles that address (EA) and byte strobes (/BE(0-3)) are held after read strobe (/ARE) or write strobe (/AWE) rising. These fields are extended by one bit on the `C6211/'C6711. Memory type `C6201/'C6202/'C6701 only: MTYPE = 000b: 8-bit-wide ROM (CE1 only) MTYPE = 001b: 16-bit-wide ROM (CE1 only) MTYPE = 010b: 32-bit-wide asynchronous interface `C6211/'C6711 only: MTYPE = 0000b: 8-bit-wide asynchronous interface MTYPE = 0001b: 16-bit-wide asynchronous interface MTYPE = 0010b: 32-bit-wide asynchronous interface Turnaround time. Controls the number of ECLKOUT cycles between a read and a write or between two reads.
TA
Clock = CLKOUT1 for `C6201/'C6202/'C6701.Clock = ECLKOUT for `C6211/'C6711. Applies to `C6211/'C6711 only.
Avoid bus contention
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MEMORY WIDTH & BYTE ALIGNMENT
Memory type ASRAM
Memory width x8 x16 x32
Maximum addressable bytes per CE space 1M 2M 4M 1M 2M 4M 32M 64M 128M
Address output on EA[21:2] A[19:0] A[20:1] A[21:2] A[19:0] A[20:1] A[21:2] See section 10.5 See section 10.5 See section 10.5
Represents
ED[31:24]
TMS320C621x/C671x ED[23:16] ED[15:8]
ED[7:0]
Byte address Halfword address Word address Byte address Halfword address Word address Byte address Halfword address Word address
32-bit device
SBSRAM
x8 x16 x32
16-bit device big endian 16-bit device little endian
SDRAM
x8 x16 x32
8-bit device big endian
8-bit device little endian
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TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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ASYNCHRONOUS INTERFACE
It uses a Intel approach: two command signals to define the access direction and validate the rest of the signals used for decoding:
Read: ARE Write: AWE
These signals define the active part of the access cycle. The rest of signals used for decoding must be stables during the active part.
Address and control signals /ARE /AWE
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ASYNCHRONOUS INTERFACE
Asynchronous read timing example (2/3/1)
Setup 2 ECLKOUT Strobe 3 Hold 1
CE BE[3:0] EA[21:2] ED[31:0] AOE ARE BE Address Read D
AWE ARDY
Active part: 3 cycles. Decoded signals are stable 2 cycles before active part. Data captured at the end of active part. Decoded signals remain stable 1 cycle after active part. RDY signal is tested at the beginning of the last cycle of the active part.
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ASYNCHRONOUS INTERFACE
Asynchronous write timing example (2/3/1)
Setup 2 ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] AOE ARE AWE ARDY BE1 A1 D1 BE2 A2 D2 Strobe 3 Hold 1 Setup 2 Strobe 3 Hold 1
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ASYNCHRONOUS INTERFACE
Ready operation: Wait state insertion
Setup 2 ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] AOE ARE AWE ARDY BE Address D Programmed strobe 4 Ready sampled Strobe extended 3 Hold 1 Data latched
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ASYNCHRONOUS INTERFACE
Turnaround Time
HOLD ECLKOUT td /CEx td /BE[3:0] td EA [21:2] tohz(m) ED [31:0] td /AOE /ARE /AWE ARDY td td td TA = 2 SETUP
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REAL WAVEFORMS: READ ACCESS
Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE/SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY 5 Read Data 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
7 6
7
Outputs: Delay time max: 7 ns
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Data capture: Setup time min: 6.5 ns Hold time min: 1 ns
ARDY test: Setup time min: 3 ns Hold time min: 2.3 ns
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REAL WAVEFORMS: WRITE ACCESS
Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
Outputs: Delay time max: 7 ns
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ARDY test: Setup time min: 3 ns Hold time min: 2.3 ns
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PROGRAMMABLE PARAMETERS
All of then are expressed as TECLKOUT units:
SETUP 1 (0 is treated as 1) STROBE 1 (0 is treated as 1) HOLD 0 TURNAROUND 0
TECLKOUT depends on system design: For DSK6713: TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
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TYPICAL APPLICATIONS
The asynchronous interface is usually used to add extend the system resources by adding:
External peripheral with parallel interface: This kind of peripherals usually have an asynchronous interface. Asynchronous memory banks: Easy design but reduced band width => restricted to non volatile memories (i.e FLASH)
We will see two examples:
Peripheral connection: A/D y D/A. Asynchronous memory banks connection.
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TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms.
Case Study I: Peripheral connection.
Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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EMIF CASE STUDY (I)
DSK interface EMIF Case Study to:
AD768 DAC. AD9220 ADC. AD9220 ADC Channel 1
DSK
E M I F
AD9220 ADC AD768 DAC AD768 DAC
Channel 2 Channel 1
Channel 2
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EMIF CASE STUDY: AD768 DAC
Specification: Case Study: AD768 DAC EMIF
FEATURES: 30 msps Update Rate 16-Bit Resolution Linearity: 1/2 LSB DNL @ 14 Bits 1 LSB INL @ 14 Bits Fast Settling: 25ns Full-Scale Settling to 0.025% SFDR @ 1 MHZ Output: 86 dBc THD @ 1 MHZ Output: 71 dBc Low Glitch Impulse: 35 pV-s Power Dissipation: 465 mW On-chip 2.5V reference Edge Triggered Latches Multiplying Reference Capability APPLICATIONS: Arbitrary Waveform Generation Communications Waveform Reconstruction Vector Stroke Display
AD768 data sheet
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EMIF CASE STUDY: AD768 DAC EMIF Case Study: Functional Block Diagram: AD768 DAC
FUNCTIONAL BLOCK DIAGRAM
DCOM VDD DB15 (MSB)
AD768
MSBs: SEGMENTED CURRENT SOURCES AND SWITCHES
MSB
DECODER and EDGETRIGGERED BIT LATCHES
LSBs: CURRENT SOURCES, SWITCHES, AND 12k R-2R LADDERS
1K 1K
INOUTA INOUTB
LADCOM
2.5 v BANDGAP REFERENCE CONTROL AMP
VEE
DB0 (LSB)
CLOCK
NC
REFCOM REFOUT IREFIN NR
AD768 data sheet
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EMIF CASE STUDY: AD768 DAC EMIF Case Study: AD768 DAC Timing:
tS = 10 ns tH = 5 ns tLPW = 10 ns
NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
AD768 data sheet
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EMIF CASE STUDY: AD768 DAC
C6713EMIF Case Study: Timing: DAC Asynchronous Write AD768
Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
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SETTING ASYNC TIMING
31
RW, +1111
28 27
22 21
Write Setup
15 TA 14 13
Write Strobe
RW, +111111
Write Hold
20 19
RW, +1111
16
Read Setup
2 0
RW, +11
8
7
4
Read Strobe
RW, + 111111
MTYPE
RW, +0010
3 Write Hold MSB
RW, +0
Read Hold
RW, +11
CE3
Set CE3 and to 32-bit ASYNC
.equ mvkl.s1 mvkh.s1 ldw nop 4 and set stw .d1 1800014h CE3, A0 CE3, A0 *A0, A1
A1, 0xff0f, A1 Note: There are more A1, 5, 5, A1 MTYPE options. See: A1, *A0 \Links\spru190d.pdf
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000b = 8-bit-wide ROM 001b = 16-bit-wide ROM 010b = 32-bit-wide Async 011b = 32-bit-wide SDRAM 100b = 32-bit-wide SBSRAM
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SETTING ASYNC TIMING EMIF Case Hardware Interface:Study: AD768 DAC
Analogue Out (Chan2) D/A Analogue Buffering
CLK /XAWE /XCE3
16
XD[0..15]
Analogue Out (Chan1)
CLK
D/A
16
XD[16..31]
AD768 data sheet
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EMIF CASE STUDY: AD768 DAC EMIF Case Study: AD9220 ADC Specifications:
FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and 10 MSPS Low Power Dissipation: 59 mW, 100 mW and 250 mW Single +5V Supply Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB Input Referred Noise: 0.09LSB Complete On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 70dB Spurious-Free Dynamic Range: 86dB Out-of-range Indicator Straight Binary Output Data 28-Lead SOIC and 28-Lead SSOP
AD9220 data sheet
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DaughtercardConnector
EMIF CASE STUDY: AD9220 ADC
Functional Block Diagram:
AD9220 data sheet
37
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EMIF CASE STUDY: AD9220 ADC EMIF Case Study: AD9220 ADC
Timing: tC = 100 ns tCH = 45 ns tCL = 45 ns tOD = 19 ns
NOTE: for DSK6713 TECLKOUT= 50 MHz => TECLKOUT = 20 ns.
AD9220 data sheet
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EMIF CASE STUDY: AD9220 ADC EMIF Case Study: AD9220 C6713 Asynchronous Read Timing: ADC
Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE/SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY 5 Read Data 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
7 6
7
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SETTING ASYNC TIMING
31
RW, +1111
28 27
22 21
Write Setup
15 TA 14 13
Write Strobe
RW, +111111
Write Hold
20 19
RW, +1111
16
Read Setup
3 2 0
RW, +11
8
Read Strobe
RW, + 111111
MTYPE Write Hold MSB
RW, +0010 RW, +0
7
4
Read Hold
RW, +011
Set CE3 and to 32-bit ASYNC
CE3 .equ mvkl.s1 mvkh.s1 ldw nop 4 and set stw .d1 1800014h CE3, A0 CE3, A0 *A0, A1 A1, 0xff0f, A1 A1, 5, 5, A1 A1, *A0
000b = 8-bit-wide ROM 001b = 16-bit-wide ROM 010b = 32-bit-wide Async 011b = 32-bit-wide SDRAM 100b = 32-bit-wide SBSRAM
Note: There are more MTYPE options. See: \Links\spru190d.pdf \Links\spru190d.pdf
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EMIF CASE STUDY: AD9220 ADC
Hardware Interface:
Analogue I n (Chan2) A/D Analogue Buffering
CLK
16
CLK /OE
XTOUT0 /XAOE /XCE3
Analogue I n (Chan1)
CLK
CLK /OE
A/D
16
Latch
16 XD[16..31]
AD9220 data sheet
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EMIF CASE STUDY: Sharing the bus
Both ADCs and DACs are mapped to the same address space (CE3 = 0xB000 0000).
16 16
XD[0..15]
A/D
CLK
DaughtercardConnector
Latch
CLK /OE
Latch
16
XD[0..15]
XTOUT0 /XAOE /XCE3
CLK
CLK /OE
A/D
Latch
16
XD[16..31]
/CE3 0 0 1
/XAOE 0 1 x
/XAWE 1 0 x
/OE 0 1 1
DAC_CLK 1 0 1
D/A
CLK
16
XD[0..15]
/XAOE activates the latched A/D output only during the read sequence
/XAWE /XCE3 CLK
D/A
16
XD[16..31]
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DaughtercardConnector
16
42
EMIF CASE STUDY: Daughter board interface
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EMIF CASE STUDY: Hardware
The INTDSK1115 daughter card from ATE Communications contains:
CODEC. 2 x ADC (AD9920). 2 x DAC (AD768).
See schematics for further details:
\Links\Schematics Page 1.pdf \Links\Schematics Page 2.pdf \Links\Schematics Page 3.pdf \Links\Schematics Page 4.pdf
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EMIF CASE STUDY: Hardware
It requires +12V, -12V and 5V power supplies:
Daughter card Connector
Pin 1 2 3 4
Signal +12V -12V DGND +5V
+12V -12V GND +5V
DSK
Warning: Do NOT supply power to J4 and J8 at the same time.
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EMIF CASE STUDY: Hardware
Procedure:
(1) Set the EMIF registers. (2) Set the internal timer to generate the sampling frequency. (3) Ensure that the DSK6211_6711.gel is loaded. (4) Write the functions for reading and writing from/to the ADC and DAC respectively. (5) Set the interrupts.
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EMIF CASE STUDY: Software EMIF EMIF Case Control Register: (1) Setting the GlobalStudy: Software - EMIF
31 16
Rsv
15
14
13
12
11
BUSREQ
10
9
8
7 NO HOLD
6
5
4
CLK1EN
3
CLK2EN
2
1
0
Rsv
Rsv
Rsv
Rsv
ARDY HOLD HOLDA
Rsv
Rsv
Rsv
Rsv
Rsv
Slight changes for `6713
0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0
3
3
0
0
The GBLCTL register is common to all spaces and can be configured as follows:
#define EMIF_GCTL 0x01800000 *(unsigned int *) EMIF_GCTL = 0x3300
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EMIF CASE STUDY: Software EMIF Setting the CE Control Register:
Which space can be used to access the ADCs? From the DSK6211_6711.gel (DSK6211_6711_gel.pdf) file we can see that the CE2 and CE3 are not used and are available on the Daughter card interface. In this application the CE3 space has been used.
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EMIF CASE STUDY: Software EMIF
Setting the CE3 Control Register:
MTYPE?
A/D 2 A/D 1 D/A 1 D/A 2
Memory
address
B0000000
32-bits
The memory is configured as 32-bit asynchronous. Therefore: MTYPE = 0010b.
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EMIF CASE STUDY: Software EMIF Setting the CE3 Control Register:
MTYPE = 0010b: 32-bit async Read/Write Hold = 011b: 3 x ECLKOUT Read/Write Strobe = 111111b: 31 x ECLKOUT Read/Write Setup = 1111b: 15 x ECLKOUT
Therefore the CE3 space can be configured as follows: Too conservative timing desing
#define EMIF_CE3 0x01800014
*(unsigned int *) EMIF_CE3 = 0xffffff23
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EMIF CASE STUDY: Software Timer
Setting the sample rate: Using the internal timer (2) Select a timer: there are two timers available, Timer 0 and Timer 1. The two internal timers are controlled by six memorymapped registers (3 registers each):
(a) Timer control registers: sets the operating modes. (b) Timer period registers: holds the number of timer clock cycles to count. (c) Timer counters: holds current value of the incrementing counter. Note: the timer clock is the CPU clock divided by 4.
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EMIF CASE STUDY: Software Timer
Register Timer control Timer period Timer counter
Address Description Timer 0 Timer 1 0x0194 0000 0x0198 0000 Sets the operating mode 0x0194 0004 0x0198 0004 Holds the number of timer clock cycles to count 0x0194 0008 0x0198 0008 Holds the current counter value
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EMIF CASE STUDY: Software Timer Initialise the timer:
CPU Frequency = FCPU = 150000000 Hz 4000 Hz
Sampling rate = SRATE =
TPRD =
FCPU 150000000 = = 468.75 4 x 2 x 4000 32000
= 0x01D5
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EMIF CASE STUDY: Software Timer
#define FCPU #define SRATE #define TPRD 150000000 /* CPU clock frequency */ 800000 /* data sample rate 800kHz */ (FCPU/(4*2*SRATE)) /* timer period, using the clock mode */ /* Handle for the timer device */
TIMER_Handle hTimer;
void start_timer1() { *(unsigned volatile int *)TIMER1_CTRL = 0x000; /* Disable output of Timer 1 */ IRQ_map(IRQ_EVT_TINT1,8); hTimer = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET); /* Configure up the timer. */ TIMER_configArgs(hTimer, TIMER_CTL_OF(0x000003c1), TIMER_PRD_OF(TPRD), TIMER_CNT_OF(0) ); /* Start Timer 1 in clock mode */ *(unsigned volatile int *)TIMER1_CTRL = 0x3C1;//clock mode /* Finally, enable the timer which will drive everything. */ TIMER_start(hTimer); }
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EMIF CASE STUDY: Loading GEL
(3) For the DSK6211 and DSK6711 select the
DSK6211_6711.gel using:
Method 1: File:Load GEL Location: ti\cc\gel\ Method 2: You can automatically execute a specific GEL function at startup as follows: (1) Select Setup CCS. (2) Select the C6x11 DSK and right click. (3) Select the "Startup GEL file(s)". (4) Type the file location as shown:
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EMIF CASE STUDY: Loading GEL
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EMIF CASE STUDY: Reading and writing to the A/D y D/A
(4) The ADC and DAC are memory-mapped and therefore can be accessed just like accessing a memory.
#define INTDSK_CE3 0xB0000000 unsigned int analogue_in = 0; unsigned int analogue_out = 0; interrupt void timerINT1 (void) { analogue_in = *(unsigned volatile int *) INTDSK_CE3; /* data processing */ ad1 = analogue_in & 0xffff0000; ad2 = analogue_in & 0x0000ffff; ad1 = ad1 << 4; ad2 = ad2 << 4; *(unsigned volatile int *) INTDSK_CE3 = analogue_out; } 57 /* mask ad2 */ /* mask ad1 */
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EMIF CASE STUDY: Setting the Interrupt (5) Timer1 is used to generate the interrupts:
The interrupt causes the execution of an ISR to take place (e.g. "InoutISR"). Procedure for setting interrupt:
(1) Map the CPU interrupt and the source:
#include #include IRQ_map (IRQ_EVT_TINIT, 8);
(2) Enable the appropriate bit of the IER: (3) (4) Enable the NMI: Enable global interrupts:
IRQ_enable (IRQ_EVT_TINT1);
IRQ_nmiEnable (); IRQ_globalEnable (); 58
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TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms. Case Study I: Peripheral connection.
Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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CASE STUDY II: ASYNC SRAM CONNECTION
CY7C1011BV33 128Kx16 15ns
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ASYNC SRAM OVERVIEW Which waveforms take into account?
Access cycle controlled by XXX signal.
Read: XXX is the last one to get active (signaling the new data appearing) and the first one to get disable (signaling its disappearing). Write: XXX is the last one to get active (the rest of the signals should be stables at this moment) and the first one to get inactive (signaling the data capture).
READ CYCLE: address controlled.
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
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CASE STUDY: ASYNC SRAM CONNECTION READ CYCLE: /OE or /BE controlled.
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE
tHZCE tHZBE
HIGH IMPEDANCE
IICC CC IISB SB
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CASE STUDY: ASYNC SRAM CONNECTION WRITE CYCLE: /CE controlled
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
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CASE STUDY: ASYNC SRAM CONNECTION WRITE CYCLE: /BE controlled
tWC ADDRESS
BHE, B LE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
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CASE STUDY: ASYNC SRAM CONNECTION WRITE CYCLE: /WE controlled, /OE low ,
tWC ADDRESS
CE
tSCE
tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE
tHA
tLZWE
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CASE STUDY: ASYNC SRAM CONNECTION Asynchronous read timing example (1/2/1)
Setup 1 ECLKOUT /CEx /BE[3:0] BE1 BE2 trc(m) td EA [21:2] A1 A2 toh(m) tacc(m) ED [31:0] /AOE td /ARE /AWE ARDY td D1 tisu D2 th td Strobe 2 Hold Setup Strobe 2 Hold 1 C6x Samples Data 1 1 'C6x Samples Data
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CASE STUDY: ASYNC SRAM CONNECTION Asynchronous write timing example (1/1/1)
Setup 1 ECLKOUT /CEx /BE[3:0] BE1 BE2 twc(m) twr(m) EA [21:2] A1 A2 td td ED [31:0] /AOE /ARE td txw(m) twp(m) /AWE ARDY td D1 D2 tih(m) Strobe 1 Hold 1 Setup 1 Strobe 1 Hold 1
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CASE STUDY: FLASH CONNECTION EMIF-Big-Endian x8 ASRAM Interface
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TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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EMIF: Other interfaces
Field Read setup Write setup Read strobe Write strobe Read hold Write hold MTYPE Description Setup width. Number of clock cycles of setup time for address (EA), chip enable (CE), and byte enables (BE[0-3]) before read strobe or write strobe falls. For asynchronous read accesses, this is also the setup time of AOE before ARE falls. Strobe width. The width of read strobe (ARE) and write strobe (AWE) in clock cycles Hold width. Number of clock cycles that address (EA) and byte strobes (BE[0-3]) are held after read strobe or write strobe rises. For asynchronous read accesses, this is also the hold time of AOE after ARE rising. Memory type of the corresponding CE spaces for C620x/C670x MTYPE Definitions for C621x/C671x/C64x MTYPE = 0000b: 8-bit-wide asynchronous interface MTYPE = 0001b: 16-bit-wide asynchronous interface MTYPE = 0010b: 32-bit-wide asynchronous interface MTYPE = 0011b: 32-bit-wide SDRAM MTYPE = 0100b: 32-bit-wide SBSRAM (C621x/C671x) 32-bit-wide programmable synchronous memory (C64x) MTYPE = 1000b: 8-bit-wide SDRAM MTYPE = 1001b: 16-bit-wide SDRAM MTYPE = 1010b: 8-bit-wide SBSRAM (C621x/C671x) 8-bit-wide programmable synchronous memory (C64x) MTYPE = 1011b: 16-bit-wide SBSRAM (C621x/C671x) 16-bit-wide programmable synchronous memory (C64x) MTYPE = 1100b: 64-bit-wide asynchronous interface (C64x only) MTYPE = 1101b: 64-bit-wide SDRAM (C64x only) MTYPE = 1110b: 64-bit-wide programmable synchronous memory (C64x only) TA Turn-around time (C621x/C671x/C64x only). Turn-around time controls the number of ECLKOUT cycles between a read, and a write, or between reads, to different CE spaces (asynchronous memory types only).
Clock cycles are in terms of CLKOUT1 for C620x/C670x, ECLKOUT for the C621x/C671x, and ECLKOUT1 for the C64x. 32-bit and 64-bit interfaces (MTYPE=0010b, 0011b, 0100b, 1100b, 1101b, 1110b) do not apply to C6712 and C64x EMIFB.
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SYNCHRONOUS SRAMs
EMIF Case Study
Double Data Rate < 200 MHz <400 MHz Data Late Write < 166 MHz Pipelined SBRAM Flow thru SBRAM < 133 MHz < 300 MHz ZBT < 166 MHz
ASRAM ASRAM < 10 MHz < 100 MHz
Not compatible C6000 Compatible Next Generation Not Planned
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SYNCHRONOUS SRAMs Asynchronous SRAMs present long critical path...
Control
Control
Address
Memory Array
Data
...and then a high access time
Control
Read A1 A2 tacc = 10 ns D2
Fast ASRAM
Address
Data
tacc = 10 ns D1
Control1
Read A1 tacc = 100 ns D1
Slow Address1 ASRAM
Data1
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SYNCHRONOUS SRAMs Solution: cut the output critical path...
Control
Control
Address
Memory Array
Data
...and adjust the input path FLOW-THROUGH SYNCRONOUS SRAM
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SYNCHRONOUS SRAMs FLOW-THROUGH SYNCRONOUS SRAM
Read:
Control Address
EMIF Case Study
B Memory Array
C
Data D
1 cycle latency
Control/Reg
A
Clock
Incompatible with EMIF
Reg
1 Clock Control (A) Address (A) Control (B) Address (B) Data (C) Data (D)
2
3
4
5
Read A1 Read A1
Read A2 Read A2 D1 D1 D2 D2
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SYNCHRONOUS SRAMs A further improvement
Control
Control
Address
Memory Array
Data
PIPELINED SYNCRONOUS SRAM
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SYNCHRONOUS SRAMs PIPELINED SYNCRONOUS SRAM
Read:
Control Address
B Memory Array
C
D
Data
2 cycles latency
Control/Reg
Reg
E
A
Clock
Reg
1 Clock Control (A) Address (A) Control (B) Address (B) Data (C) Data (D) Data (E) 2 3 4 5
A B
Read A1 Read A1
Read A2 Read A2 D1 D2 D1 D2 D1 D2
C
D E
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PIPELINED SYNCHRONOUS SRAMs
EMIF Case Study
MT58128L32P1 128Kx32 225 MHz
Burst control SA0,SA1,SA ADSP ADSC ADV MODE BW[3:0] BWE GW CE CE2 CE2 OE CLK DQ[31:0]
Address bus
SA0, SA1, SA
Chip enable
/CE, CE2, /CE2
Data bus
DQ[31:0]
Output enable
/OE
Burst control
#ADSP, #ADSC #ADV, MODE
CLK.
Chip Write enable control
Write control
#BW[3:0], #BWE #GW
FEATURES:
Burst access. One cycle Deselect for READ access.
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PIPELINED SYNCHRONOUS SRAMs
EMIF Case Study PIPELINED SYNCRONOUS SRAM: BURST MODE
Address Clk
Address Latch
2 A0 A1 2
Upper Address bits
CLK
=
Third Address Fourth Address
Lower 2 Address bits
First Address
Second Address
ADV
2-bit Counter
Mode
ADV=0 CLK
ADV=0 CLK
=
ADV=0 CLK
=
=
It allows the automatic generation of the next address. Linear or interleaved increment. It automatically rolls over to 00 from 11.
if address 0111b were issued in burst mode, the subsequent access would be to 0100b. => Error!
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PIPELINED SYNC SRAMs: READ CYCLE
t KC
EMIF Case Study
t KL
CLK
t KH t ADSS tADSH
ADSP#
t ADSS tADSH
ADSC#
t AS tAH
ADDRESS
A1
t WS tWH
A2
A3 Burst continued with new base address. Deselect (NOTE 4) cycle.
GW#, BWE#, BWa#-BWd#
t CES tCEH
CE# (NOTE 2) ADV#
t AAS
tAAH
ADV# suspends burst. OE# (NOTE 3)
t KQLZ t OEHZ t OEQ t OELZ t KQ t KQX t KQHZ
Q
High-Z
t KQ
Q(A1)
Q(A2) (NOTE 1)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURSTREAD
Burst wraps around to its initial state.
DON'T CARE
UNDEFINED
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PIPELINED SYNC SRAMs: WRITE CYCLE
t KC
EMIF Case Study
t KL
CLK
t KH t ADSS tADSH
ADSP#
t ADSS t ADSH
ADSC# extends burst.
t ADSS tADSH
ADSC#
t AS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP# initiates burst.
A3
t WS tWH
BWE#, BWa#-BWd# (NOTE 5)
t WS tWH
GW#
t CES t CEH
CE# (NOTE 2) ADV# (NOTE 4) OE# (NOTE 3)
t DS tDH
t AAS
tAAH
ADV# suspends burst.
D Q
High-Z
D(A1)
tOEHZ
D(A2)
D(A2 + 1) (NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON'T CARE UNDEFINED
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EMIF: SYNC. BURST SRAM INTERFACE Read deselect. Burst access, linear increment.
Roll over correction: If address 0111b were issued in burst mode, the subsequent access would be to 0100b. => Error!
Case 1 SBSRAM Address EMIF Address First address A[1:0] EA[3:2] 00 01 10 Fourth Address 11 Case 2 A[1:0] EA[3:2] 01 10 11 00 Case 3 A[1:0] EA[3:2] 10 11 00 01 Case 4 A[1:0] EA[3:2] 11 00 01 10
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SYNCHRONOUS BURST SRAM INTERFACE
EMIF Case word Read Example: sixStudyread
Read ECLKOUT CE BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE BE1 BE2 BE3 BE4 BE5 BE6 Read/D1 D2 latched latched D3 latched D4 latched D6 D5 latched latched/deselect
EA[4:2]=010b D1 D2
EA[4:2]=100b D3 D4 D5 D6
010
011 100
101
110
111
100
10
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SYNCHRONOUS BURST SRAM INTERFACE
EMIF Case word Write Example: sixStudywrite
Write ECLKOUT CEx BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE D1 BE1 BE2 BE3 BE4 BE5 BE6 Write Deselect
EA[4:2]=000b D2 D3 D4
EA[4:2]=100b D5 D6
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REAL WAVEFORMS EMIF Case Study READ ACCESS
ECLKOUT 1 CEx BE[3:0] EA[21:2] 6 ED[31:0] 8 SSADS 9 SSOE SSWE 9 8 Q1 2 BE1 4 EA 7 Q2 Q3 Q4 3 BE2 BE3 5 BE4 1
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REAL WAVEFORMS EMIF Case Study WRITE ACCESS
ECLKOUT 1 CEx BE[3:0] 2 BE1 4 EA[21:2] ED[31:0] 10 Q1 8 SSADS SSOE 12 SSWE 12 8 Q2 EA 11 Q3 Q4 3 BE2 BE3 5 BE4 1
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CONNECTION
EMIF Case Study
MT58L128L36 128Kx32 225 MHz
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TIMING
EMIF Case Study External clock interface:
E ECLKOUT tdmax 'C6211 /'C6711 tdmin E
Output from DSP: Data Bus, Control and Address:
Tcyc EMIF Clock tih(m) tisu(m) tdmin SBSRAM Latches Data Tcyc
tdmax 'C6000 Outputs
Input to DSP: Data Bus:
Tcyc EMIF Clock tsu tacc(m) Read Data tih toh(m) 'C6x Latches Data Tcyc
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TMS320C6000 FAMILY: EMIF
Introduction.
Characteristics, signals, memory map, alignment. Configuration registers. Types of interface.
Asynchronous interface.
Introduction, waveforms. Case Study I: Peripheral connection. Case Study II: Memory connection.
Interface with synchronous static memories.
Synchronous static memories. Interface description. Example.
Interface with synchronous dynamic memories.
SDRAM memories. Interface description. Example.
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EMIF: SDRAM INTERFACE
TO BE ADDED...
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FINAL
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